The Zig Runtime Engine

Hardware-Agnostic native Speed

Traditional PLCs rely on specialized hardware ASICs and vendor operating systems. PAML decouples logic from silicon by executing within a sandboxed WebAssembly (WASI) virtual machine wrapper compiled in Zig. This allows the runtime engine to execute natively on any commodity SBC (such as NanoPi or Raspberry Pi) or virtualized Linux node, bypassing hypervisors to run at hardware speed.

Cache-Line Alignment (Lock-Free Processing)

In multi-core processing, thread contention is the primary bottleneck. If Core 1 (safety) writes to a register that Core 2 (control) is reading on the same CPU cache block, the processor core stalls. PAML structures the global I/O memory matrix in Zig using 64-byte alignment buffers, guaranteeing that concurrent cores calculate equations in parallel without memory locks:

/// Align memory to the processor's native 64-byte L1 cache boundaries
const CacheAlignedRegister = struct {
    value: f32,
    raw_unscaled: u16,
    status_flags: u8,
    padding: [57]u8, // Pad structure out to perfectly match a 64-byte hardware footprint
} align(64);

Thread-Isolated Priority Domains

At boot, the Zig engine maps PAML statements into separate memory arrays sorted by priority. It then binds execution threads to specific physical CPU cores using hardware affinity tools (like `pthread_setaffinity_np`):

• Core 1 (Safety Domain): Executes priority `(A)` statements on a tight, deterministic 1ms cycle window. Bitwise calculations are prioritized here.
• Core 2 & 3 (Control Domain): Processes priority `(B)` continuous loops and PID constants on a 10ms cycle. Floating-point registers are updated here.
• Core 4 (Analytics Domain): Processes priority `(C)` batch state transitions and downsampling rules on a 100ms cycle, serialization, and network dispatch.

LTTB Data Historian Downsampling

Traditional historians stream raw time-series data to central databases, where Swinging Door algorithms compress it. This is computationally expensive and frequently strips out fast transient spikes (such as an over-pressure safety trip) if tolerances are misconfigured.

The PAML Zig runtime incorporates LTTB (Largest Triangle Three Buckets) downsampling directly into the edge memory buffer. LTTB divides high-frequency data into temporal buckets and preserves visual-invariant coordinates (high-low spikes), writing compressed chunks directly to local parquet files in S3-compatible buckets:

pub fn lttbCompress(allocator: std.mem.Allocator, input: []const DataPoint, threshold: usize) ![]DataPoint {
    // Splits time-series arrays into 'threshold' buckets
    // Selects coordinates that maximize the triangular area between adjacent buckets
    // Preserves visual fidelity of transient spikes on zoom-out HMI charts
}

Direct Kernel-Bypassing Network I/O

To eliminate network latency stack overhead, the virtual PLC interacts directly with the network interface card (NIC) using **AF_XDP raw sockets**. When an Ethernet TSN (Time-Sensitive Networking) frame containing sensor packets arrives, the NIC injects the data directly into the shared `ProcessValueRegistry` RAM offsets via DMA, completing the transit-to-logic step in under 500 microseconds.